The present invention relates to a voltage regulator for outputting a constant voltage, and in particular to stabilization of the output voltage at the time of switching.
FIG. 2 shows a conventional voltage regulator.
The illustrated voltage regulator is for supplying a display drive voltage VD to a boosting circuit 2 generating a boosted voltage VP to be supplied to a display panel 1, and comprises a first voltage generating circuit 4 for generating a first output voltage VA, and a second voltage generating circuit 3 for generating a second output voltage VB. The first voltage generating circuit 4 comprises a reference voltage generator 10, a bias circuit 20, a differential amplifier 30, and an output circuit 40.
The output terminal of the output circuit 40 is connected via a first switch 5 to an output node NO. The output terminal of the second voltage generating circuit 3 is connected via a second switch 6 to the output node NO. The first switch 5 is controlled by a control signal EN, while the second switch 6 is controlled by an inverted control signal /EN obtained by inverting the control signal EN by an inverter 7.
The reference voltage generator 10 generates and outputs a reference voltage VR when it is permitted to operate (or activated) by the control signal EN. The bias circuit 20 outputs a bias voltage BL to the differential amplifier 30 and the output circuit 40 when it is permitted to operate (activated) by the control signal EN. The bias voltage BL is for causing a predetermined current to flow through the differential amplifier 30, and for causing a predetermined current to flow through the output circuit 40.
The differential amplifier 30 amplifies the difference between the reference voltage VR supplied from the reference voltage generator 10, and the output voltage VA of the output circuit 40, and controls the output circuit 40, so that the output voltage VA becomes equal to the reference voltage VR. The differential amplifier 30 comprises N-channel MOS transistors (hereinafter referred to as “NMOS”) 31 and 32 with their gates supplied with the reference voltage VR and the output voltage VA, respectively. The sources of the NMOS's 31 and 32 are connected to the ground potential node GND via an NMOS 33 controlled by the bias voltage BL. The drains of the NMOS's 31 and 32 are connected to the nodes N31 and N32, respectively.
The nodes N31 and N32 are connected to the power supply potential node VDD via P-channel MOS transistors (hereinafter referred to as “PMOS”) 34 and 35, respectively. The gates of the PMOS 34 and 35 are connected to the node N32.
The output circuit 40 has a PMOS 41 connected between a node N41 at which the output voltage VA appears, and the power supply potential node VDD, and having its gate connected to the node N31, and an NMOS 42 connected between the node N41 and the ground potential node GND, and having its gate supplied with the bias voltage BL. The node N41 and the node N31 are coupled by a series connection of a resistor 43 and a capacitor 44 for phase compensation.
In the voltage regulator shown in FIG. 2, when the control signal EN is at a level “L” (ground potential GND), the reference voltage generator 10 and the bias circuit 20 are prohibited to operate (or deactivate) and the reference voltage VR from the reference voltage generator 10 is at “L”, and the bias voltage BL output from the bias circuit 20 is set to “L”. The NMOS's 33 and 42 are OFF, and the differential amplifier 30 and the output circuit 40 are also prohibited to operate. Moreover, the control signal EN at “L” will cause the first switch 5 to be OFF, and the second switch 6 to be ON. The output voltage VB from the second voltage generating circuit 3 is supplied via the second switch 6 to the output node NO, as a drive voltage VD.
When the control signal EN is at a level “H” (power supply potential VDD), the reference voltage generator 10 and the bias circuit 20 operate (are activated), and the bias voltage BL output from the bias circuit 20 causes the differential amplifier 30 and the output circuit 40 to operate (to be activated). Moreover, when the control signal EN is at “H”, the first switch 5 is ON, and the second switch 6 is OFF. As a result, the output voltage VA from the output circuit 40 is supplied via the first switch 5 to the output node NO, as the drive voltage VD.
Another circuit for generating a constant voltage, with a switching circuit for switching between an external normal power supply and a backup power supply, is shown in Japanese Patent Kokai Publication No. 2002-91575.
The above-described voltage regulator has the following problems. When the control signal EN is changed from “L” to “H”, the first and second switches 5 and 6 respond promptly, and the first switch 5 is turned ON and the second switch 6 is turned OFF. As a result, the output voltage VB which has been output from the second voltage generating circuit 3 to the output node NO is promptly interrupted. On the other hand, the output voltage VA output from the output circuit 40 will not be at a normal voltage until the operation of the reference voltage generator 10, the bias circuit 20 and the differential amplifier 30 is stabilized. As a result, the voltage at the output node NO is unstable, immediately after the switching, and the display quality of the display panel 1 is lowered.